1. Technical Field
This invention relates in general to memory cell redundancy in semiconductor memories and, more particularly, to devices and methods for repairing semiconductor memories by replacing memory blocks that contain failing memory cells with redundant rows or columns of cells.
2. State of the Art
Semiconductor memories generally include a multitude of memory cells arranged in rows and columns. Each memory cell is capable of storing digital information in the form of a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d bit. To write (i.e., store) a bit into a memory cell, a binary memory address having portions identifying the cell""s row (the xe2x80x9crow addressxe2x80x9d) and column (the xe2x80x9ccolumn addressxe2x80x9d) is provided to addressing circuitry in the semiconductor memory to activate the cell, and the bit is then supplied to the cell. Similarly, to read (i. e., retrieve) a bit from a memory cell, the cell is again activated using the cell""s memory address, and the bit is then output from the cell.
Semiconductor memories are typically tested after they are fabricated to determine if they contain any failing memory cells (i.e., cells to which bits cannot be dependably written or from which bits cannot be dependably read). Generally, when a semiconductor memory is found to contain failing memory cells, an attempt is made to repair the memory by replacing the failing memory cells with redundant memory cells provided in redundant rows or columns in the memory.
Conventionally, when a redundant row is used to repair a semiconductor memory containing a failing memory cell, the failing cell""s row address is permanently stored (typically in pre-decoded form) on a chip on which the semiconductor memory is fabricated by programming a non-volatile element (e.g., a group of fuses, anti-fuses, or FLASH memory cells) on the chip. Then, during normal operation of the semiconductor memory, if the memory""s addressing circuitry receives a memory address including a row address that corresponds to the row address stored on the chip, redundant circuitry in the memory causes a redundant memory cell in the redundant row to be accessed instead of the memory cell identified by the received memory address. Since every memory cell in the failing cell""s row has the same row address, every cell in the failing cell""s row, both operative and failing, is replaced by a redundant memory cell in the redundant row.
Similarly, when a redundant column is used to repair the semiconductor memory, the failing cell""s column address is permanently stored (typically in pre-decoded form) on the chip by programming a non-volatile element on the chip. Then, during normal operation of the semiconductor memory, if the memory""s addressing circuitry receives a memory address including a column address that corresponds to the column address stored on the chip, redundant circuitry in the memory causes a redundant memory cell in the redundant column to be accessed instead of the memory cell identified by the received memory address. Since every memory cell in the failing cell""s column has the same column address, every cell in the failing cell""s column, both operative and failing, is replaced by a redundant memory cell in the redundant column.
Thus, for example, as shown in FIG. 1, a semiconductor memory 20 having failing memory cells 22, 24, 26, 28, 30, 32, 34, and 36 is repaired in the conventional manner described above using redundant rows 38, 40, and 42 and redundant columns 44, 46, and 48. As described above, the memory 20 is repaired by replacing all memory cells in columns 50, 52, and 54, including failing memory cells 22, 24, 26, and 28, with redundant memory cells in redundant columns 44, 46, and 48. Further repairs to the memory 20 are accomplished by replacing all memory cells in rows 56, 58, and 60, including failing memory cells 30, 32, 34, and 36, with redundant memory cells in redundant rows 38, 40, and 42.
The process described above for repairing a semiconductor memory using redundant rows and columns is well known in the art, and is described in various forms in U.S. Pat. Nos. 4,459,685, 4,601,019, 5,422,850, and 5,528,539.
Unfortunately, it is difficult to provide enough redundant rows or columns in a semiconductor memory to repair all failing memory cells therein using the conventional repair process described above without using an excessive amount of space (commonly known as xe2x80x9creal estatexe2x80x9d) in the memory for the redundant rows or columns. With the increasing size of semiconductor memories continuously increasing the need for redundancy, memory designers find themselves caught between providing sufficient redundancy to successfully repair most memories and, as a result, using excessive space in the memories, or providing insufficient redundancy to save space in the memories and, as a result, having to discard memories that are unrepairable. Obviously, neither alternative is desirable.
U.S. Pat. No. 5,548,225 to Rountree et al. discloses a repair system that, in contrast to the conventional repair system described above, does not use an entire redundant row or column to repair each defective memory cell in a semiconductor memory. In the Rountree repair system, the column address of a defective memory cell is stored using fuses in the same manner as described above. In addition, though, a partial row address common to a group of cells in the defective cell""s column that includes the defective cell itself is also stored using fuses. When a memory address is received having column and row addresses that match the stored column address and stored partial row address, a redundant memory cell in a spare column is accessed. As a result, all of the cells in the group identified by the stored column address and stored partial row address are replaced by redundant cells in the spare column, while those cells in the defective cell""s column not in the identified group are not replaced. Thus, the efficiency of repairs is increased by the Rountree system because only some of the redundant cells in the spare column are used to repair the defective cell, while other redundant cells remain in the spare column to repair other defective cells.
Unfortunately, the Rountree repair system can be problematic as well, because storing a full column address and a partial row address for every defective memory cell in need of repair requires a great deal of storage space (e.g., fuses, etc.). Consequently, the ever-increasing size of modern semiconductor memories, and the corresponding increase in the number of defective memory cells typically found, makes the Rountree repair system increasingly prohibitive to use because of the amount of storage space it requires.
Therefore, there is a need in the art for an improved device and method for repairing a semiconductor memory containing a failing memory cell. Such a device and method should replace the failing cell with a redundant memory cell without replacing the failing cell""s entire row or column with the redundant cell""s entire row or column. The device should also replace multiple failing cells in different rows or columns with redundant memory cells in a single redundant row or column in order to make more efficient use of redundant rows and columns, and should do so without the excessive need for storage space characteristic of the Rountree repair system.
A block repair device in accordance with the present invention is used in a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), having a primary array with a defective cell and a redundant array with a redundant row. The block repair device includes a set of non-volatile elements, such as fuses, anti-fuses, or flash EEPROM cells, that store a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of the repair block used to repair the defective cell. Routing circuitry, such as mux circuitry, in the block repair device is configured by the block repair configuration to output some received row and column address bits in a selected ratio. Comparison circuitry in the block repair device then compares the row and column address bits output by the routing circuitry with a stored portion of the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array.
The present invention thus provides an efficient device for implementing block repairs in a semiconductor memory. The device requires relatively few fuses or other non-volatile elements to implement a repair, in contrast to the Rountree and other conventional methods described above.
In other embodiments of the invention, the block repair device described above is incorporated into a semiconductor memory, a semiconductor substrate, such as a wafer, a DRAM, and an electronic system.
In a block repair method according to the present invention, a semiconductor memory having a primary array with a defective cell and a redundant array with a redundant row is repaired using a block repair. The dimensions of a repair block within the primary array for repairing the defective cell are first selected, and those row and column address bits of the defective cell that define the selected dimensions of the repair block are then stored using, for example, non-volatile elements within the semiconductor memory. A block repair configuration that corresponds to the selected dimensions of the repair block is also stored using, for example, non-volatile elements. Those received row and column address bits necessary to determine whether a received address falls within the repair block are then routed in accordance with the stored block repair configuration for comparison with the stored row and column address bits of the defective cell. When a match occurs, memory operations within the primary array are temporarily disabled, the redundant row is fired, and data is then written to or read from a cell within the redundant row selected in accordance with non-stored row and column address bits of the defective cell.